[Mips] R5900 scheduling model and FP cost fixes #15

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techwritescode merged 5 commits from r5900-sched-coverage into r5900-ee 2026-10-15 19:52:30 +00:00

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techwritescode commented 2026-10-15 18:51:50 +00:00

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R5900 scheduling and cost-model changes from PS2-192. All are gated on the R5900 subtarget; no generic pass, pipeline or -O meaning changes.

Commit	Change	Console result
Schedule R5900 stores apart at -O2	Scheduler alias analysis and post-RA scheduling at -O2 for R5900	packet_build 1.11x to 0.95x GCC -O2 cycles
FP arithmetic latency in the cost model	add.s/sub.s/mul.s/neg.s report 4 cycles; no FP cmov, so float ifs stay branches	with the next commit: physics (loops swapped) 1.38x to 1.13x GCC -O2
Keep FP arithmetic ahead of FP branches, narrowed by the follow-up commit	Mips shouldSink keeps FP arithmetic in a block that ends in bc1t/bc1f, so it fills the measured ~6-cycle c.cond.s to branch gap; past integer branches it sinks as usual	see above
Cover the R5900 instructions the compiler emits	Measured entries for unaligned loads/stores, teq, 64-bit ALU, div $zero, 64-bit branches	model coverage for sdk-core EE libs

Measured split on physics with loops swapped (-O2): 2.32M baseline, 2.07M with the cost model alone (1.23x GCC), 1.89M with both (1.13x). The narrowed hook gives the same 1.89M, and the bench compiles to identical code before and after narrowing.

Code size of the bench is unchanged. 2023 lit tests pass (CodeGen/Mips, MC/Mips, MC/Disassembler/Mips, Transforms/SimplifyCFG).

🤖 Generated with Claude Code

R5900 scheduling and cost-model changes from PS2-192. All are gated on the R5900 subtarget; no generic pass, pipeline or -O meaning changes. | Commit | Change | Console result | |---|---|---| | Schedule R5900 stores apart at -O2 | Scheduler alias analysis and post-RA scheduling at -O2 for R5900 | packet_build 1.11x to 0.95x GCC -O2 cycles | | FP arithmetic latency in the cost model | add.s/sub.s/mul.s/neg.s report 4 cycles; no FP cmov, so float ifs stay branches | with the next commit: physics (loops swapped) 1.38x to 1.13x GCC -O2 | | Keep FP arithmetic ahead of FP branches, narrowed by the follow-up commit | Mips `shouldSink` keeps FP arithmetic in a block that ends in `bc1t`/`bc1f`, so it fills the measured ~6-cycle `c.cond.s` to branch gap; past integer branches it sinks as usual | see above | | Cover the R5900 instructions the compiler emits | Measured entries for unaligned loads/stores, teq, 64-bit ALU, div $zero, 64-bit branches | model coverage for sdk-core EE libs | Measured split on physics with loops swapped (-O2): 2.32M baseline, 2.07M with the cost model alone (1.23x GCC), 1.89M with both (1.13x). The narrowed hook gives the same 1.89M, and the bench compiles to identical code before and after narrowing. Code size of the bench is unchanged. 2023 lit tests pass (CodeGen/Mips, MC/Mips, MC/Disassembler/Mips, Transforms/SimplifyCFG). 🤖 Generated with [Claude Code](https://claude.com/claude-code)

techwritescode added 4 commits 2026-10-15 18:51:50 +00:00

[Mips] Schedule R5900 stores apart at -O2 ... 5fd5e5e17e

The R5900 pairs a store only with a non-store. Enable alias analysis in
the scheduler and post-RA scheduling at -O2 for the R5900 so a loop's
independent stores are spread among its ALU work. On the console this
takes the packet_build bench from 1.11x to 0.95x GCC's cycles at -O2
with no change in code size.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

[Mips] Give R5900 FP arithmetic its latency in the cost model ... 0c0472d5b8

R5900 add.s, sub.s, mul.s and neg.s take 4 cycles, and the FPU has no
conditional move, so a float select costs a compare and a branch. Report
the latency for TCK_Latency and TCK_SizeAndLatency so SimplifyCFG keeps a
short float if as a branch instead of turning it into selects.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

[Mips] Keep R5900 FP arithmetic ahead of FP branches ... 4a58cdb398

The R5900 takes about six cycles from c.cond.s to bc1t/bc1f. Stop
MachineSink moving FP arithmetic below the branch, so it runs in that gap.
Together with the cost model change this takes the physics bench, with its
loops swapped to stay in cache, from 1.38x to 1.13x GCC's cycles at -O2,
with no change in code size.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

[Mips] Cover the R5900 instructions the compiler emits ... 4e69b0b4e3

Compiling sdk-core's EE libraries showed opcodes the R5900 model left at
the default one-cycle, no-resource entry: the 64-bit ALU forms, the
unaligned loads and stores, teq, the div $zero forms and the 64-bit
compare-with-zero branches. Measured on the console: lwl/lwr/ldl/ldr and
their stores issue once per cycle on the load/store unit with load
latency; teq and the 64-bit ALU forms dual-issue with latency 1; div
$zero then mflo takes 36.75 cycles, teq adding nothing.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

techwritescode referenced this pull request 2026-10-15 19:10:58 +00:00

[Mips] Select the R5900's integer movz and movn #16

techwritescode referenced this pull request from ps2/sdk-core 2026-10-15 19:34:25 +00:00

tests/bench: interrupts-off timing and updated GCC vs LLVM results #34

techwritescode referenced this pull request from a commit 2026-10-15 19:34:25 +00:00

tests/bench: record results with ps2/llvm#15 and #16, explain the exceptions

techwritescode referenced this pull request from a commit 2026-10-15 19:42:17 +00:00

tests/bench: record results with ps2/llvm#15 and #16, explain the exceptions

techwritescode added 1 commit 2026-10-15 19:51:24 +00:00

[Mips] Keep R5900 FP arithmetic only ahead of FP branches ... 13a8e1a86b

The c.cond.s to bc1t/bc1f gap (about six cycles, measured on the console)
only exists in a block that ends in an FP branch. Stop sinking FP
arithmetic only there, and let MachineSink move it as usual past integer
branches. The bench compiles to the same code at -O1 to -Os, and physics
with its loops swapped still runs in 1.89M cycles at -O2.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

techwritescode merged commit 13a8e1a86b into r5900-ee 2026-10-15 19:52:30 +00:00

techwritescode deleted branch r5900-sched-coverage 2026-10-15 19:52:31 +00:00

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