tests/bench: interrupts-off timing and updated GCC vs LLVM results #34

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techwritescode merged 2 commits from bench-timing into main 2026-10-15 19:43:58 +00:00

PS2-192 items 2 and 7.

  • Every bench kernel now runs best of 3 inside DIntr/EIntr. Before, all kernels ran with interrupts on, and physics and raster ran once. physics and raster reset their input before each run, so the checksums are unchanged (physics 46fb9806, raster c8cb2e87, packet_build 67522a17).
  • The README now has console results with ps2/llvm#15 and #16, and the cause of each gap over 5%: cache-set conflicts in physics, per-pixel branches in raster, constant propagation into static callees for the -O1 size gaps. It also documents that raster varies between boots by up to 7%, so raster figures are the minimum over 3 to 7 boots.

🤖 Generated with Claude Code

PS2-192 items 2 and 7. - Every bench kernel now runs best of 3 inside `DIntr`/`EIntr`. Before, all kernels ran with interrupts on, and physics and raster ran once. physics and raster reset their input before each run, so the checksums are unchanged (physics 46fb9806, raster c8cb2e87, packet_build 67522a17). - The README now has console results with ps2/llvm#15 and #16, and the cause of each gap over 5%: cache-set conflicts in physics, per-pixel branches in raster, constant propagation into static callees for the -O1 size gaps. It also documents that raster varies between boots by up to 7%, so raster figures are the minimum over 3 to 7 boots. 🤖 Generated with [Claude Code](https://claude.com/claude-code)
physics and raster ran once with interrupts on. All kernels now run three
times inside DIntr/EIntr, and physics and raster reset their input before
each run so the checksums are unchanged.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
tests/bench: record results with ps2/llvm#15 and #16, explain the exceptions
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2bdc0a7e34
physics is dominated by cache-set conflicts between its six arrays; raster
varies between boots; the -O1 size gaps come from constant propagation into
static callees.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
techwritescode force-pushed bench-timing from 2bdc0a7e34
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2026-10-15 19:42:17 +00:00
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techwritescode deleted branch bench-timing 2026-10-15 19:43:59 +00:00
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