[Mips] Select the R5900's integer movz and movn #16

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techwritescode merged 1 commit from r5900-cmov into r5900-ee 2026-10-15 19:55:46 +00:00

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techwritescode commented 2026-10-15 19:10:58 +00:00

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Stacked on ps2/llvm#15 (base r5900-sched-coverage); retarget to r5900-ee once #15 is merged.

The R5900 implements the integer MIPS IV conditional moves (movz, movn) but LLVM models it as MIPS III, so every integer select became a branch. This enables them for the R5900 in instruction selection, the assembler and the disassembler. The FPU conditional moves (movz.s, movn.s, movt, movf) stay unavailable, as on the hardware. GCC already uses movz/movn for -march=r5900. Gated on FeatureR5900; other CPUs are unchanged.

Bench function size, LLVM/GCC	-O1	-O2	-O3	-Os
raster, before	1.14	0.84	0.96	1.25
raster, after	1.09	0.81	0.89	1.19
all kernels, before	0.96	0.88	0.78	0.92
all kernels, after	0.94	0.86	0.75	0.90

On the console all checksums match. Speed is unchanged at -O1, -O2 and -O3 (raster minimum over 2 to 4 boots within 0.1%). At -Os the raster pixel loop is the same instructions at a different address (setup got shorter), and the result is not settled: raster shows per-boot modes for every compiler, and this build gave 8.11M cycles on 7 of 7 boots against 7.63M to 7.89M before; with fb 4 KB-aligned it gave 7.54M on 1 of 4 boots and 8.11M on the others. GCC -Os is 9.37M to 9.62M.

Tests: CodeGen/Mips/r5900-cmov.ll, MC/Mips/r5900-cmov.s (including the MIPS III rejection and the FPU forms staying invalid), MC/Disassembler/Mips/r5900-cmov.txt. All 2026 tests in CodeGen/Mips, MC/Mips, MC/Disassembler/Mips and Transforms/SimplifyCFG pass.

🤖 Generated with Claude Code

Stacked on ps2/llvm#15 (base `r5900-sched-coverage`); retarget to `r5900-ee` once #15 is merged. The R5900 implements the integer MIPS IV conditional moves (`movz`, `movn`) but LLVM models it as MIPS III, so every integer select became a branch. This enables them for the R5900 in instruction selection, the assembler and the disassembler. The FPU conditional moves (`movz.s`, `movn.s`, `movt`, `movf`) stay unavailable, as on the hardware. GCC already uses `movz`/`movn` for `-march=r5900`. Gated on `FeatureR5900`; other CPUs are unchanged. | Bench function size, LLVM/GCC | -O1 | -O2 | -O3 | -Os | |---|---|---|---|---| | raster, before | 1.14 | 0.84 | 0.96 | 1.25 | | raster, after | 1.09 | 0.81 | 0.89 | 1.19 | | all kernels, before | 0.96 | 0.88 | 0.78 | 0.92 | | all kernels, after | 0.94 | 0.86 | 0.75 | 0.90 | On the console all checksums match. Speed is unchanged at -O1, -O2 and -O3 (raster minimum over 2 to 4 boots within 0.1%). At -Os the raster pixel loop is the same instructions at a different address (setup got shorter), and the result is not settled: raster shows per-boot modes for every compiler, and this build gave 8.11M cycles on 7 of 7 boots against 7.63M to 7.89M before; with `fb` 4 KB-aligned it gave 7.54M on 1 of 4 boots and 8.11M on the others. GCC -Os is 9.37M to 9.62M. Tests: `CodeGen/Mips/r5900-cmov.ll`, `MC/Mips/r5900-cmov.s` (including the MIPS III rejection and the FPU forms staying invalid), `MC/Disassembler/Mips/r5900-cmov.txt`. All 2026 tests in CodeGen/Mips, MC/Mips, MC/Disassembler/Mips and Transforms/SimplifyCFG pass. 🤖 Generated with [Claude Code](https://claude.com/claude-code)

techwritescode added 1 commit 2026-10-15 19:10:59 +00:00

[Mips] Select the R5900's integer movz and movn ... b6eaff4ae6

The R5900 implements the MIPS IV integer conditional moves but is modelled
as MIPS III, so integer selects were lowered to branches. Enable movz and
movn for the R5900 in codegen, the assembler and the disassembler; the FPU
conditional moves (movz.s, movn.s, movt, movf) stay unavailable. GCC uses
these instructions for -march=r5900. On the console the bench checksums
match, speed is unchanged, and bench function size drops by 2 to 3 points
at every level (raster -Os from 1.25x to 1.19x GCC).

Co-Authored-By: Claude Opus 5.5 <[email protected]>

techwritescode force-pushed r5900-cmov from b6eaff4ae6 to db4a34fca9 2026-10-15 19:13:10 +00:00 Compare

techwritescode changed target branch from r5900-sched-coverage to r5900-ee 2026-10-15 19:52:31 +00:00

techwritescode force-pushed r5900-cmov from db4a34fca9 to 5c05831eb6 2026-10-15 19:55:13 +00:00 Compare

techwritescode merged commit 5c05831eb6 into r5900-ee 2026-10-15 19:55:46 +00:00

techwritescode deleted branch r5900-cmov 2026-10-15 19:55:47 +00:00

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