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[Mips] R3000A: shared select diamonds and branchless i64 orderings #23

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techwritescode merged 3 commits from r3000a-delay-slots into r3000a-load-delay 2026-10-16 19:51:05 +00:00
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techwritescode commented 2026-10-16 19:47:22 +00:00
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Stacked on r3000a-load-delay (#22). Both changes are gated on isR3000A().

  • Consecutive selects on the same condition (the halves of an i64 select) share one branch diamond with several PHIs, instead of one diamond each.
  • i64 orderings (lt/le/gt/ge, signed and unsigned) lower through custom SETCCCARRY and USUBO using a borrow chain, with no branches. mips1 is unchanged.

Lit tests: r3000a-select-pair.ll, r3000a-i64-compare.ll. Full CodeGen/Mips and MC/Mips lit pass.

Measured on the console rig (minimum over 3 boots), checksums identical across builds. Ticks, #22 vs this branch: crc 79375/79375, sort 153696/153696, decode 84630/84630, div 38650/38650, state 69029/69029, str 135796/135796, lba (new i64 select and compare kernel) 121845/96122. Nothing is slower than #22. The IRX total over the 89 sdk-core IRXs is 1,216 bytes smaller.

Not fixed, because only a generic pass or a new delay-slot filler feature would close them: sort loop strength reduction, remaining load-delay and branch-slot nops, and the lw $ra; nop; jr epilogue (a real load-use dependency). i64 == via xor/xor/or is the same size as GCC's per-word branches.

🤖 Generated with Claude Code

Stacked on r3000a-load-delay (#22). Both changes are gated on isR3000A(). - Consecutive selects on the same condition (the halves of an i64 select) share one branch diamond with several PHIs, instead of one diamond each. - i64 orderings (lt/le/gt/ge, signed and unsigned) lower through custom SETCCCARRY and USUBO using a borrow chain, with no branches. mips1 is unchanged. Lit tests: r3000a-select-pair.ll, r3000a-i64-compare.ll. Full CodeGen/Mips and MC/Mips lit pass. Measured on the console rig (minimum over 3 boots), checksums identical across builds. Ticks, #22 vs this branch: crc 79375/79375, sort 153696/153696, decode 84630/84630, div 38650/38650, state 69029/69029, str 135796/135796, lba (new i64 select and compare kernel) 121845/96122. Nothing is slower than #22. The IRX total over the 89 sdk-core IRXs is 1,216 bytes smaller. Not fixed, because only a generic pass or a new delay-slot filler feature would close them: sort loop strength reduction, remaining load-delay and branch-slot nops, and the `lw $ra; nop; jr` epilogue (a real load-use dependency). i64 `==` via xor/xor/or is the same size as GCC's per-word branches. 🤖 Generated with [Claude Code](https://claude.com/claude-code) 
Without conditional moves each select becomes a branch diamond. Consecutive
selects on one condition, such as the halves of an i64 select, now use a
single diamond with several PHIs.

Co-Authored-By: Claude Sonnet 5.5 <[email protected]>
[Mips] Lower R3000A i64 orderings without branches
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90831b04b5 
The generic expansion compares the high words and selects between the low and
high results, which costs two branches. Expand through SETCCCARRY instead:
(Hi1 < Hi2) | ((Hi1 - Hi2) <u LoBorrow), with the low borrow as a plain sltu.

Co-Authored-By: Claude Sonnet 5.5 <[email protected]>
[Mips] Drop explanatory comments from the R3000A select and compare lowering
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3d1f4b5e16 
Co-Authored-By: Claude Sonnet 5.5 <[email protected]>
techwritescode merged commit 3d1f4b5e16 into r3000a-load-delay 2026-10-16 19:51:05 +00:00
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