[Mips] R3000A load-delay scheduling: post-RA at -O2/-Os, LWL/LWR pairs (PS2-193) #22

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techwritescode merged 6 commits from r3000a-load-delay into r5900-ee 2026-10-16 19:55:29 +00:00

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techwritescode commented 2026-10-16 15:00:01 +00:00

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Two R3000A-gated changes from PS2-193 (IOP code size and timing against GCC). Both rest on how the R3000A's load delay works.

Commit	Change
Run the post-RA scheduler for the R3000A at -O2 and -Os	getOptLevelToEnablePostRAScheduler returned Default only for the R5900. The R3000A has a scheduling model (LoadLatency 2), so the post-RA scheduler now also runs at -O2/-Os, where IOP modules are built, and fills load delay slots with independent work.
Let an R3000A LWL/LWR pair share the load delay	The R3000A merges an LWL and an LWR to the same register through the load delay, so the second load needs no nop in front of it. Gated on the R3000A: the upstream unalignedload.ll PSX (-mcpu=mips1) checks keep their nop.

New tests: CodeGen/Mips/r3000a-postra-sched.ll (with and without -post-RA-scheduler=false) and CodeGen/Mips/r3000a-lwl-lwr-delay.ll (R3000A without the nop, mips1 with it).

Effect, measured on the 904 sdk-core IOP objects (PS2-193 comments): nops 33,130 down to 31,622; IRX total from +8.7% to +8.3% against GCC. Timing on the console is not measured yet.

Verified: llvm-lit CodeGen/Mips MC/Mips, 1552 tests, 0 failures. That run was on the local branch r3000a-postra-sched, which also carries two more R3000A commits that are not in this PR (see below). These two changes do not depend on them.

Held back for review against the fork rule (UPDATING.md, "What belongs in the fork"), still local on r3000a-postra-sched:

• -Os inlining threshold for the R3000A lowered to the -Oz value (-2.9% IRX size). A threshold change.
• Tail merging for the R3000A, with a sink-hi16 pass added before it so HI16/LO16 pairs stay together (-1.5%). Adds a target pass to the pipeline.

🤖 Generated with Claude Code

Two R3000A-gated changes from PS2-193 (IOP code size and timing against GCC). Both rest on how the R3000A's load delay works. | Commit | Change | |---|---| | Run the post-RA scheduler for the R3000A at -O2 and -Os | `getOptLevelToEnablePostRAScheduler` returned Default only for the R5900. The R3000A has a scheduling model (LoadLatency 2), so the post-RA scheduler now also runs at -O2/-Os, where IOP modules are built, and fills load delay slots with independent work. | | Let an R3000A LWL/LWR pair share the load delay | The R3000A merges an LWL and an LWR to the same register through the load delay, so the second load needs no nop in front of it. Gated on the R3000A: the upstream `unalignedload.ll` PSX (`-mcpu=mips1`) checks keep their nop. | New tests: `CodeGen/Mips/r3000a-postra-sched.ll` (with and without `-post-RA-scheduler=false`) and `CodeGen/Mips/r3000a-lwl-lwr-delay.ll` (R3000A without the nop, mips1 with it). Effect, measured on the 904 sdk-core IOP objects (PS2-193 comments): nops 33,130 down to 31,622; IRX total from +8.7% to +8.3% against GCC. Timing on the console is not measured yet. Verified: `llvm-lit CodeGen/Mips MC/Mips`, 1552 tests, 0 failures. That run was on the local branch `r3000a-postra-sched`, which also carries two more R3000A commits that are not in this PR (see below). These two changes do not depend on them. Held back for review against the fork rule (UPDATING.md, "What belongs in the fork"), still local on `r3000a-postra-sched`: - -Os inlining threshold for the R3000A lowered to the -Oz value (-2.9% IRX size). A threshold change. - Tail merging for the R3000A, with a sink-hi16 pass added before it so HI16/LO16 pairs stay together (-1.5%). Adds a target pass to the pipeline. 🤖 Generated with [Claude Code](https://claude.com/claude-code)

techwritescode added 2 commits 2026-10-16 15:00:01 +00:00

[Mips] Run the post-RA scheduler for the R3000A at -O2 and -Os ... 4095235c52

The R3000A scheduling model separates loads from their users, but the
post-RA scheduler only ran at -O3 for every CPU but the R5900. On the sdk-core
IOP modules at -Os this removes about 1,500 of the load-delay nops and shrinks
the IRX total from +8.7% to +8.3% over GCC.

Co-Authored-By: Claude Sonnet 5.5 <[email protected]>

[Mips] Let an R3000A LWL/LWR pair share the load delay ... e4fc85dd91

The R3000A merges an LWL and an LWR to the same register through the load
delay, so the second load needs no nop in front of it. Gated on the R3000A;
other MIPS I CPUs keep the nop. Tests cover this and the post-RA scheduler
change.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

techwritescode added 1 commit 2026-10-16 15:38:08 +00:00

[Mips] Limit the R3000A post-RA scheduler to one instruction per cycle ... fe782f0019

The R3000A has no itinerary, so the post-RA list scheduler got a hazard
recognizer with no issue limit and put several instructions in one cycle.
It then used up independent instructions before a jump-table load was
ready and left the load right before the jump, which costs a load-delay
nop. A single-issue hazard recognizer for the R3000A fixes the order.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

techwritescode commented 2026-10-16 19:12:06 +00:00

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New commit fe782f0: limit the R3000A post-RA scheduler to one instruction per cycle.

The R3000A has no itinerary, so the post-RA list scheduler got the default hazard recognizer, which never limits issue. It put several instructions in one "cycle", spent the independent ones before a jump-table load was ready, and left the load directly before jr, which costs a load-delay nop. On the console the IOP state-machine kernel got 6% slower with the post-RA change alone. A single-issue hazard recognizer, gated on the R3000A, fixes it. Test: CodeGen/Mips/r3000a-postra-single-issue.ll, which fails without the fix. r3000a-postra-sched.ll is updated for the new order.

Lit on this branch (separate build of r3000a-load-delay): CodeGen/Mips + MC/Mips, 1553 tests, 0 failures.

Results for this branch against r5900-ee 5c05831:

	Baseline	This PR
89 sdk-core IRXs, total bytes	1,608,028 (+8.73% vs GCC)	1,595,372 (+7.88% vs GCC), -0.79%

IOP kernel timing on the console, IOP system clock ticks, minimum over 3 boots:

Kernel	GCC	Baseline	This PR	PR/baseline
crc	88417	83347	79375	0.95
sort	133145	150384	150831	1.00
decode	76324	86092	84061	0.98
div	53144	39148	38650	0.99
state	66266	69062	69062	1.00
str	147678	142430	134828	0.95

No kernel is slower than the baseline. sort is 1.13x GCC with or without this PR: GCC ends the inner loop with bne against a hoisted -1, while LLVM's loop strength reduction uses a separate counter and needs slti + beqz. That choice is made in a generic pass, so it is left as a documented exception.

New commit fe782f0: limit the R3000A post-RA scheduler to one instruction per cycle. The R3000A has no itinerary, so the post-RA list scheduler got the default hazard recognizer, which never limits issue. It put several instructions in one "cycle", spent the independent ones before a jump-table load was ready, and left the load directly before `jr`, which costs a load-delay nop. On the console the IOP state-machine kernel got 6% slower with the post-RA change alone. A single-issue hazard recognizer, gated on the R3000A, fixes it. Test: `CodeGen/Mips/r3000a-postra-single-issue.ll`, which fails without the fix. `r3000a-postra-sched.ll` is updated for the new order. Lit on this branch (separate build of `r3000a-load-delay`): CodeGen/Mips + MC/Mips, 1553 tests, 0 failures. Results for this branch against r5900-ee 5c05831: | | Baseline | This PR | |---|---|---| | 89 sdk-core IRXs, total bytes | 1,608,028 (+8.73% vs GCC) | 1,595,372 (+7.88% vs GCC), -0.79% | IOP kernel timing on the console, IOP system clock ticks, minimum over 3 boots: | Kernel | GCC | Baseline | This PR | PR/baseline | |---|---|---|---|---| | crc | 88417 | 83347 | 79375 | 0.95 | | sort | 133145 | 150384 | 150831 | 1.00 | | decode | 76324 | 86092 | 84061 | 0.98 | | div | 53144 | 39148 | 38650 | 0.99 | | state | 66266 | 69062 | 69062 | 1.00 | | str | 147678 | 142430 | 134828 | 0.95 | No kernel is slower than the baseline. sort is 1.13x GCC with or without this PR: GCC ends the inner loop with `bne` against a hoisted -1, while LLVM's loop strength reduction uses a separate counter and needs `slti` + `beqz`. That choice is made in a generic pass, so it is left as a documented exception.

techwritescode referenced this pull request 2026-10-16 19:47:22 +00:00

[Mips] R3000A: shared select diamonds and branchless i64 orderings #23

techwritescode added 3 commits 2026-10-16 19:51:06 +00:00

[Mips] Share one branch diamond between R3000A selects with the same condition ... 0dbccd4ee3

Without conditional moves each select becomes a branch diamond. Consecutive
selects on one condition, such as the halves of an i64 select, now use a
single diamond with several PHIs.

Co-Authored-By: Claude Sonnet 5.5 <[email protected]>

[Mips] Lower R3000A i64 orderings without branches ... 90831b04b5

The generic expansion compares the high words and selects between the low and
high results, which costs two branches. Expand through SETCCCARRY instead:
(Hi1 < Hi2) | ((Hi1 - Hi2) <u LoBorrow), with the low borrow as a plain sltu.

Co-Authored-By: Claude Sonnet 5.5 <[email protected]>

[Mips] Drop explanatory comments from the R3000A select and compare lowering ... 3d1f4b5e16

Co-Authored-By: Claude Sonnet 5.5 <[email protected]>

techwritescode merged commit 3d1f4b5e16 into r5900-ee 2026-10-16 19:55:29 +00:00

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